On July 3, 2025, the Department of Science and Technology of the Ministry of Industry and Information Technology (MIIT) issued notice to call for public feedback on drafts for approval of 6 national voluntary standards, and five of them are regarding the interconnection interface specification for chiplets (hereinafter referred to as “the Chiplet Standards”). The call for comment period was ended on July 10, 2025.
The Chiplet Standards were approved by the National Standardization Administration of China (SAC) in June of 2024, and SAC/TC599 (Integrated circuits) are in charge of the formulation and relevant works. According to the information that have been acquired, the main drafters of these standards are mostly Chinese enterprises (such as Hisilicon, a company under Huawei, and JCET Group etc.), universities (Peking University and Tsinghua University etc.), and sector alliance named Zhongguancun Technical Alliance on High-performance Chop Interncoonection, and national standardization institution such as the China Electronics Standardization Institute (CESI) etc.
The formulation of the Chiplet Standards is not only a response to the tasks assigned in the Key Working Points of National Standardization 2024, but also based on the consideration that: i) the computing revolution brought by emerging technologies such as big data, cloud computing and AI calls for higher requirements for chips, yet the computational power of present chips has nearly reached its maximum, and the cost for advanced chips stays in a high level; ii) chiplet offers a possibility to achieve high performance with reasonable cost; iii) The development of chiplet and its package has reached to a certain level that requires standardization works, which is also expected to guide and support a further development within the country.
Key information of the Chiplet Standards is summarized as below:
No. | Project No. | Standard Name | Main Content |
2 | 20242059-T-339 | Specification for Chiplet Interconnection Interface Part 1: General Principles | It defines the terms and definitions, abbreviations of the chiplet interconnect interface, stipulates the hierarchical architecture of the chiplet interconnect interface and the basic functions of each layer, and establishes the interconnect scenarios and encapsulation types |
3 | 20242056-T-339 | Specification for Chiplet Interconnection Interface Part 2: Protocol Layer Technical Requirements | It specifies the technical requirements for the protocol layer of the chiplet interconnect interface, and also specifies the message format adaptation methods for the general SoC bus protocol, high-bandwidth storage protocol, and custom protocols |
4 | 20242062-T-339 | Specification for Chiplet Inerconnection Interface Part 3: Data Link Layer Technical Requirements | It specifies the technical requirements for the data link layer of the chiplet interconnect interface, including: transmission message format, data error detection and correction mechanism, as well as technical requirements related to link state and power consumption management |
5 | 20242060-T-339 | Specification for Chiplet Inerconnection Interface Part 4: Physical Layer Technical Requirements Based on 2D Package | It specifies the physical layer technical requirements for the chiplet interconnect interface based on 2D package, including the initialization and training process, physical layer electrical specifications, redundancy mechanism, interface physical layout, and low-power control. |
6 | 20242067-T-339 | Specification for Chiplet Inerconnection Interface Part 5: Physical Layer Technical Requirements Based on 2.5D Package | It specifies the technical requirements for the physical layer based on 2.5D package, including initialization and training processes, electrical characteristics of the physical layer, redundancy mechanisms, physical layout of interface, and low-power control |
Relevant foreign stakeholders are advised to notice that based on requirements of China on the national standard formulation time period, these five standards may be finished and published later this year or early next year. However, if the collected public feedback shows it necessary to further modify the draft, the publication may be delayed to a later time. Another tricky part for foreign stakeholders is that, the full text of the drafts for approval of the Chiplet Standards, meaning the most recent version of the standard text after the drafts for comments, are publicized on the official website of the China Electronics Standardization Association (CESA) at: https://www.cesa.cn/approval?nipId=140. But their access requires being a member of the Association and the text are not downloadable without login as a member.
Additional information on SAC/TC599
Founded in April of 2023, the TC is in charge of the standardization works in regards of the design, production and application of integrated circuit equipment, semiconductor integrated circuits, thin-film integrated circuits and hybrid thin-film integrated circuits, microwave integrated circuits, circuit modules, integrated circuit chips and intellectual property modules (IP cores), and micro-electromechanical systems (MEMS), etc.
SAC/TC599 is the mirror committee of China for IEC/SC47D and IEC/SC47F.
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